1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for filling contact openings and vias with copper to create copper interconnections and lines.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires reducing the size and cross-sectional dimensions of electrical interconnects to contacts to active areas, such as N+ (P+) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor, and the like. As the size and cross-sectional dimensions of electrical interconnects get smaller, resistance increases and electromigration increases. Increased resistance and electromigration are undesirable for a number of reasons. For example, increased resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor. Additionally, electromigration effects in aluminum (Al) interconnects, where electrical currents actually carry aluminum (Al) atoms along with the current, causing them to electromigrate, may lead to degradation of the aluminum (Al) interconnects, further increased resistance, and even disconnection and/or delamination of the aluminum (Al) interconnects.
The ideal interconnect conductor for semiconductor circuitry will be inexpensive, easily patterned, have low resistivity, and high resistance to corrosion, electromigration, and stress migration. Aluminum (Al) is most often used for interconnects in contemporary semiconductor fabrication processes primarily because aluminum (Al) is inexpensive and easier to etch than, for example, copper (Cu). However, because aluminum (Al) has poor electromigration characteristics and high susceptibility to stress migration, it is typical to alloy aluminum (Al) with other metals.
As discussed above, as semiconductor device geometries shrink and clock speeds increase, it becomes increasingly desirable to reduce the resistance of the circuit metallization. The one criterion that is most seriously compromised by the use of aluminum (Al) for interconnects is that of conductivity. This is because the three metals with lower resistivities (aluminum, Al, has a resistivity of 2.824xc3x9710xe2x88x926 ohms-cm at 20xc2x0 C.), namely, silver (Ag) with a resistivity of 1.59xc3x9710xe2x88x926 ohms-cm (at 20xc2x0 C.), copper (Cu) with a resistivity of 1.73xc3x9710xe2x88x926 ohms-cm (at 20xc2x0 C.), and gold (Au) with a resistivity of 2.44xc3x9710xe2x88x926 ohms-cm (at 20xc2x0 C.), fall short in other significant criteria. Silver (Ag), for example, is relatively expensive and corrodes easily, and gold (Au) is very costly and difficult to etch. Copper (Cu), with a resistivity nearly on par with silver (Ag), a relatively high immunity to electromigration, high ductility and high melting point (1083xc2x0 C. for copper, Cu, vs. 660xc2x0 C. for aluminum, Al), fills most criteria admirably. However, copper (Cu) is difficult to etch in a semiconductor environment. As a result of the difficulty in etching copper (Cu), an alternative approach to forming vias and metal lines must be used. The damascene approach, consisting of etching openings such as trenches in the dielectric for lines and vias and creating in-laid metal patterns, is the leading contender for fabrication of sub-0.25 micron (sub-0.25xcexc) design rule copper-metallized (Cu-metallized) circuits.
However, even with copper (Cu) interconnects, high mechanical stress levels in the copper (Cu) interconnects and lines may (1) give rise to the formation of stress-induced voids, and (2) decrease the reliability of the copper (Cu) interconnects and lines, both of which effects are undesirable. Typically, mechanical stress levels in aluminum (Al) interconnects and lines are controlled by adjusting the deposition temperature of a subsequently deposited interlevel (or interlayer) dielectric (ILD) layer. For example, as described in U.S. Letters Patent No. 5,789,315, entitled xe2x80x9cEliminating Metal Extrusions By Controlling the Liner Deposition Temperature,xe2x80x9d issued Aug. 4, 1998, assigned by the inventors Paul R. Besser et al. to Advanced Micro Devices, Inc., the assignee of the present application, hereby incorporated in its entirety by reference herein, as if set forth below, the deposition temperature of a conformal dielectric layer is controlled relative to a subsequent degas temperature, thereby lowering thermal compressive stresses in previously formed aluminum (Al) interconnects and lines.
Mechanical stresses in metallic interconnects and lines typically arise from the difference in thermal expansion between the metallic interconnects and lines, on the one hand, and the underlying and/or adjacent semiconducting substrate and/or dielectric layer(s), on the other hand, which rigidly confine the metallic interconnects and lines. The magnitude of the mechanical stress can be determined using X-ray diffraction (XRD) techniques. The aluminum (Al) interconnects and lines are typically produced by patterning blanket-deposited films using known photolithographic patterning techniques and a subtractive etching process, such as a reactive ion etch (RIE) process. When the aluminum (Al) interconnects and lines are subsequently heated to the temperature (typically about 400xc2x0 C.) at which the passivation layer, such as an interlayer dielectric (ILD) layer is deposited, the mechanical stress state of the aluminum (Al) interconnects and lines is small or effectively zero. After deposition of the passivation layer, large hydrostatic (or isotropic) mechanical stresses in the aluminum (Al) interconnects and lines develop as the aluminum (Al) tries to contract more than the adjacent passivation layer and/or the underlying semiconducting substrate will permit.
The mechanical stresses in the aluminum (Al) interconnects and lines behave linearly with temperature, since normal plastic deformation cannot relieve a hydrostatic mechanical stress. The mechanical stresses in the aluminum (Al) interconnects and lines are larger than the aluminum (Al) yield mechanical stresses, but cannot be relieved by simple plastic deformation mechanisms since the aluminum (Al) interconnects and lines are under hydrostatic tensile mechanical stresses. For aluminum (Al) interconnects and lines, mechanical stress-induced voiding has been observed as one way that these large mechanical stresses get relieved. Consequently, such mechanical stress-induced voiding is a reliability concern for aluminum (Al) interconnects and lines.
As described above, damascene-fabricated copper (Cu) may be used to replace aluminum (Al) as the interconnect metallization for high-performance logic technologies as critical dimensions approach about 0.22 microns (xcexcm) and 0.18 microns (xcexcm), and smaller. This is due, in part, to the higher conductivity, improved electromigration performance and reduced cost of manufacturing of damascene-fabricated copper (Cu). As was the experience with aluminum (Al), the fabrication method strongly influences the mechanical stress state. As described above, even with copper (Cu) interconnects, high mechanical stress levels in the copper (Cu) interconnects and lines may (1) give rise to the formation of stress-induced voids, and (2) decrease the reliability of the copper (Cu) interconnects and lines, both of which effects are undesirable. Consequently, there is a need to better control and reduce mechanical stress level in copper (Cu) interconnects and lines used in integrated circuits.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided, the method comprising forming a first dielectric layer above a first structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure above the first dielectric layer and in the first opening. The method also comprises annealing the first copper structure using one of a furnace anneal process performed at a temperature ranging from approximately 100-400xc2x0 C. for a time ranging from approximately 10-90 minutes and a rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 100-400xc2x0 C. for a time ranging from approximately 10-180 seconds.